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Xilinx.com/XC5202-3PG156I
{"VIH Min. (CMOS) (V)":"3.5","V(OL)Max.(V)Lo Level Out.Volt.":".4","Digital Input V Max (V)":"7","Vsup(+) Nom.(V) Pos.Sup.Volt.":"5","Quiescent Current Max (TTL)":"15m","Pins":"156","@Iol (A)":"8m","Logic Level Family":"CMOS and T","Quiescent Current Max (CMOS)":"15m","Package Body Material":"Ceramic","Gate Capacity":"3000","VIL Max. (TTL) (V)":".8","Package":"PGA","VIH Min. (TTL) (V)":"2.0","@IOH (test)":"8m","Configurable Logic Blocks":"64","Military":"N","Number of User I/Os":"84","V(OH)Min.(V)Hi Level O...
1166 Bytes - 03:43:55, 17 November 2024
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| XC5202-3PQG100C.pdf | 0.65 | 1 | Request | |
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| XC5202-3PCG84I.pdf | 0.65 | 1 | Request | |
| XC5202-3PQ100I.pdf | 0.65 | 1 | Request | |
| XC5202-3PC84I.pdf | 0.65 | 1 | Request | |
| XC5202-3PCG84C.pdf | 0.65 | 1 | Request |
