ion Capability with Silicon Explorer II * Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) * Secure Programming Technology Prevents Reverse Engineering and Design Theft SX - A P r od u ct P r o f i l e Device A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 16,000 24,000 32,000 48,000 72,000 108,000 Logic Modules Combinatorial Cells 768 512 1,452 924 2,880 1,800 6,036 4,024 Register Cells Dedicated Flip-Flops Maximum Flip-Flops 256 512 528 990 1,080 1,980 2,012 4,024 Maximum User I/Os 130 180 249 360 3 3 3 3 Capacity Typical Gates System Gates Global Clocks Quadrant Clocks Boundary Scan Testing 0 0 0 4 Yes Yes Yes Yes 3.3V/5.0V PCI Yes Yes Yes Yes Clock-to-Out 4.2 ns 4.6 ns 4.7 ns 5.8 ns Input Set-Up (External) Speed Grades Temperature Grades Package (by pin count) PQFP TQFP PBGA FBGA F eb r u a r y 2 0 0 1 (c) 2001 Actel Corporation 0 ns 0 ns 0 ns 0 ns -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 C, I C, I, M C, I, M C, I, M 208 100, 144 --

Input Tolerance and 5 V Drive Strength Very Low Power Consumption Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Boundary-Scan Testing in Compliance with IEEE 1149.1 (JTAG) A54SX32A A54SX72A Capacity Typical Gates System Gates 32,000 48,000 72,000 108,000 Logic Modules Combinatorial Cells 2,880 1,800 6,036 4,024 Register Cells Dedicated Flip-Flops Maximum Flip-Flops 1,080 1,980 2,012 4,024 Maximum User I/Os 228 213 Global Clocks 3 3 Quadrant Clocks 0 4 Yes Yes Boundary-Scan Testing 3.3 V / 5 V PCI Yes Yes Clock-to-Out 5.3 ns 6.7 ns 0 ns 0 ns Std, -1 Std, -1 84, 208, 256 208, 256 Input Set-Up (External) Speed Grades Package (by Pin Count) CQFP N o ve m b e r 2 0 0 6 (c) 2006 Actel Corporation i See the Actel website for the latest version of the datasheet. HiRel SX-A Family FPGAs Ordering Information A54SX32A - 1 CQ M 208 Application (Ambient Temperature Range) M = Military (-55 to +125C) B = MIL-STD-883 Class B Package Lead

rse Engineering and Design Theft Table 1 * SX-A Product Profile Device Capacity Typical Gates System Gates Logic Modules Combinatorial Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 16,000 24,000 32,000 48,000 72,000 108,000 768 512 256 512 1 1,452 924 528 990 2,880 1,800 1,080 1,980 6,036 4,024 2,012 4,024 130 180 249 360 3 3 3 3 0 0 0 4 Boundary Scan Testing Yes Yes Yes Yes 3.3 V / 5 V PCI Yes Yes Yes Yes Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns -F, Std, -1, -2 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 Temperature Grades C, I, A, M C, I, A, M C, I, A, M C, I, A, M Package (by pin count) PQFP TQFP PBGA FBGA CQFP 208 100, 144 - 144 - 208 100, 144 - 144, 256 - 208 100, 144, 176 329 144, 256, 484 208, 256 208 - - 256, 484 208, 256 Speed Grades2 Notes: 1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers. 2. All -3 speed grades hav

con Explorer II * Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) * Actel's Secure Programming Technology with FuseLockTM Prevents Reverse Engineering and Design Theft SX - A P r od u ct P r o f i l e Device A54SX08A A54SX16A A54SX32A A54SX72A Capacity Typical Gates 8,000 16,000 32,000 72,000 System Gates 12,000 24,000 48,000 108,000 Logic Modules 768 1,452 2,880 6,036 Combinatorial Cells 512 924 1,800 4,024 Register Cells Dedicated Flip-Flops 256 528 1,080 2,012 Maximum Flip-Flops 512 990 1,980 4,024 Maximum User I/Os 130 180 249 360 Global Clocks 3 3 3 3 Quadrant Clocks 0 0 0 4 Boundary Scan Testing Yes Yes Yes Yes 3.3V/5V PCI Yes Yes Yes Yes Clock-to-Out 4.2 ns 4.6 ns 4.7 ns 5.8 ns Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns Speed Grades -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 Temperature Grades C, I, A C, I, M, A C, I, M, A C, I, M, A Package (by pin count) 208 208 PQFP 208 208 100, 144 100, 144, 176 -- TQFP 100, 144 329 -- -- -- PB

ue In-System Diagnostic and Verification Capability with Silicon Explorer IJ Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Secure Programming Technology Prevents Reverse Engineering and Design Theft Device A54SX08A A54SX16A A54SX32A A54SX72A Capacity Typical Gates 8,000 16,000 32,000 72,000 System Gates 12,000 24,000 48,000 108,000 Logic Modules 768 1,452 2,880 6,036 Combinatorial Cells 512 924 1,800 4,024 Register Cells Dedicated Flip-Flops 256 528 1,080 2,012 Maximum Flip-Flops 512 990 1,980 4,024 Maximum User I/Os 130 180 249 360 Global Clocks 3 3 3 3 Quadrant Clocks 0 0 0 4 Boundary Scan Testing Yes Yes Yes Yes 3.3V/5.0V PCI Yes Yes Yes Yes Clock-to-Out 4.2 ns 4.6ns 4.7 ns 5.8 ns Input Set-Up (External) Ons Ons Ons Ons Speed Grades -F, Std, -1,-2,-3 -F, Std,-1,-2,-3 -F, Std,-1,-2,-3 -F, Std, -1,~2,-3 Temperature Grades C, | C,1,M C,1,M C,1,M Package (by pin count) PQFP 208 208 208 208 TQFP 100, 144 100, 144 100, 144, 176 PBGA 329 _ FBGA 144 144, 256 144, 256, 484 256, 4

ion Capability with Silicon Explorer II * Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) * Secure Programming Technology Prevents Reverse Engineering and Design Theft SX - A P r od u ct P r o f i l e Device A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 16,000 24,000 32,000 48,000 72,000 108,000 Logic Modules Combinatorial Cells 768 512 1,452 924 2,880 1,800 6,036 4,024 Register Cells Dedicated Flip-Flops Maximum Flip-Flops 256 512 528 990 1,080 1,980 2,012 4,024 Maximum User I/Os 130 180 249 360 3 3 3 3 Capacity Typical Gates System Gates Global Clocks Quadrant Clocks Boundary Scan Testing 0 0 0 4 Yes Yes Yes Yes 3.3V/5.0V PCI Yes Yes Yes Yes Clock-to-Out 4.2 ns 4.6 ns 4.7 ns 5.8 ns Input Set-Up (External) Speed Grades Temperature Grades Package (by pin count) PQFP TQFP PBGA FBGA M a r c h 20 0 1 (c) 2001 Actel Corporation 0 ns 0 ns 0 ns 0 ns -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 C, I C, I, M C, I, M C, I, M 208 100, 144 -- 144 20

rse Engineering and Design Theft Table 1 * SX-A Product Profile Device Capacity Typical Gates System Gates Logic Modules Combinatorial Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 16,000 24,000 32,000 48,000 72,000 108,000 768 512 256 512 1 1,452 924 528 990 2,880 1,800 1,080 1,980 6,036 4,024 2,012 4,024 130 180 249 360 3 3 3 3 0 0 0 4 Boundary Scan Testing Yes Yes Yes Yes 3.3 V / 5 V PCI Yes Yes Yes Yes Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns -F, Std, -1, -2 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 Temperature Grades C, I, A, M C, I, A, M C, I, A, M C, I, A, M Package (by pin count) PQFP TQFP PBGA FBGA CQFP 208 100, 144 - 144 - 208 100, 144 - 144, 256 - 208 100, 144, 176 329 144, 256, 484 208, 256 208 - - 256, 484 208, 256 Speed Grades2 Notes: 1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers. 2. All -3 speed grades hav

ith Silicon Explorer II Boundary-Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Actel Secure Programming Technology with FuseLockTM Prevents Reverse Engineering and Design Theft Table 1 * SX-A Product Profile Device A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 16,000 24,000 32,000 48,000 72,000 108,000 Logic Modules Combinatorial Cells Dedicated Flip-Flops Maximum Flip-Flops 768 512 256 512* 1,452 924 528 990 2,880 1,800 1,080 1,980 6,036 4,024 2,012 4,024 Maximum User I/Os 130 180 249 360 3 3 3 3 Capacity Typical Gates System Gates Global Clocks Quadrant Clocks 0 0 0 4 Boundary Scan Testing Yes Yes Yes Yes 3.3 V / 5 V PCI Yes Yes Yes Yes Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns -F, Std, -1, -2 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 Temperature Grades C, I, A, M C, I, A, M C, I, A, M C, I, A, M Package (by pin count) PQFP TQFP PBGA FBGA CQFP 208 100, 144 - 144 - 208 100, 144 - 144, 256 - 208 100, 144, 176 329 144, 256, 484 208, 256 208 - - 256, 484 208, 25

les Combinatorial Cells Register Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks Boundary Scan Testing 3.3V PCI Speed Grades Temperature Grades* Package (by pin count) PQFP TQFP FBGA A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 768 512 16,000 24,000 1,452 924 32,000 48,000 2,880 1,800 72,000 108,000 6,036 4,024 256 512 130 3 0 Yes Yes Std A 528 990 180 3 0 Yes Yes Std A 1,080 1,980 249 3 0 Yes Yes Std A 2,012 4,024 360 3 4 Yes Yes Std A 208 100, 144 144 208 100, 144 144, 256 208 100, 144 144, 256 208 - 256, 484 Note: *The SX-A family is also offered in commercial, industrial and military temperature grades with -F, -1, -2 and -3 speed grades, in addition to the Std speed grade. Refer to the SX-A Family FPGAs datasheet and HiRel SX-A Family FPGAs datasheet for more details. September 2003 (c) 2003 Actel Corporation i SX-A Automotive Family FPGAs Ordering Information A54SX16A PQ 208 A Application (Temperature Range) A = Automotive (-40C to 125C) Pac

les Combinatorial Cells Register Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks Boundary Scan Testing 3.3V PCI Speed Grades Temperature Grades* Package (by pin count) PQFP TQFP FBGA A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 768 512 16,000 24,000 1,452 924 32,000 48,000 2,880 1,800 72,000 108,000 6,036 4,024 256 512 130 3 0 Yes Yes Std A 528 990 180 3 0 Yes Yes Std A 1,080 1,980 249 3 0 Yes Yes Std A 2,012 4,024 360 3 4 Yes Yes Std A 208 100, 144 144 208 100, 144 144, 256 208 100, 144 144, 256 208 - 256, 484 Note: *The SX-A family is also offered in commercial, industrial and military temperature grades with -F, -1, -2 and -3 speed grades, in addition to the Std speed grade. Refer to the SX-A Family FPGAs datasheet and HiRel SX-A Family FPGAs datasheet for more details. May 2006 (c) 2006 Actel Corporation i SX-A Automotive Family FPGAs Ordering Information A54SX16A PQ 208 A Application (Temperature Range) A = Automotive (-40C to 125C) Package L

rse Engineering and Design Theft Table 1 * SX-A Product Profile Device Capacity Typical Gates System Gates Logic Modules Combinatorial Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 16,000 24,000 32,000 48,000 72,000 108,000 768 512 256 512 1 1,452 924 528 990 2,880 1,800 1,080 1,980 6,036 4,024 2,012 4,024 130 180 249 360 3 3 3 3 0 0 0 4 Boundary Scan Testing Yes Yes Yes Yes 3.3 V / 5 V PCI Yes Yes Yes Yes Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns -F, Std, -1, -2 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 Temperature Grades C, I, A, M C, I, A, M C, I, A, M C, I, A, M Package (by pin count) PQFP TQFP PBGA FBGA CQFP 208 100, 144 - 144 - 208 100, 144 - 144, 256 - 208 100, 144, 176 329 144, 256, 484 208, 256 208 - - 256, 484 208, 256 Speed Grades2 Notes: 1. A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers. 2. All -3 speed grades hav

con Explorer II * Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) * Actel's Secure Programming Technology with FuseLockTM Prevents Reverse Engineering and Design Theft SX - A P r od u ct P r o f i l e Device A54SX08A A54SX16A A54SX32A A54SX72A Capacity Typical Gates 8,000 16,000 32,000 72,000 System Gates 12,000 24,000 48,000 108,000 Logic Modules 768 1,452 2,880 6,036 Combinatorial Cells 512 924 1,800 4,024 Register Cells Dedicated Flip-Flops 256 528 1,080 2,012 Maximum Flip-Flops 512 990 1,980 4,024 Maximum User I/Os 130 180 249 360 Global Clocks 3 3 3 3 Quadrant Clocks 0 0 0 4 Boundary Scan Testing Yes Yes Yes Yes 3.3V/5V PCI Yes Yes Yes Yes Clock-to-Out 4.2 ns 4.6 ns 4.7 ns 5.8 ns Input Set-Up (External) 0 ns 0 ns 0 ns 0 ns Speed Grades -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 -F, Std, -1, -2, -3 Temperature Grades C, I, A C, I, M, A C, I, M, A C, I, M, A Package (by pin count) 208 208 PQFP 208 208 100, 144 100, 144, 176 -- TQFP 100, 144 329 -- -- -- PB

les Combinatorial Cells Register Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks Boundary Scan Testing 3.3V PCI Speed Grades Temperature Grades* Package (by pin count) PQFP TQFP FBGA A54SX08A A54SX16A A54SX32A A54SX72A 8,000 12,000 768 512 16,000 24,000 1,452 924 32,000 48,000 2,880 1,800 72,000 108,000 6,036 4,024 256 512 130 3 0 Yes Yes Std A 528 990 180 3 0 Yes Yes Std A 1,080 1,980 249 3 0 Yes Yes Std A 2,012 4,024 360 3 4 Yes Yes Std A 208 100, 144 144 208 100, 144 144, 256 208 100, 144 144, 256 208 - 256, 484 Note: *The SX-A family is also offered in commercial, industrial and military temperature grades with -F, -1, -2 and -3 speed grades, in addition to the Std speed grade. Refer to the SX-A Family FPGAs datasheet and HiRel SX-A Family FPGAs datasheet for more details. June 2006 (c) 2006 Actel Corporation i SX-A Automotive Family FPGAs Ordering Information A54SX16A PQ 208 G A Application (Temperature Range) A= Automotive (-40C to 125C) Package

Cadence, Exemplar, IST, Mentor Graphics, Model Technology, Synopsys, Synplicity, and Viewlogic Design Entry and Simulation Tools * Secure Programming Technology Prevents Reverse Engineering and Design Theft SX-A Product Profile A54SX08A A54SX16A A54SX32A A54SX72A Typical Gates 8,000 16,000 32,000 72,000 System Gates 12,000 24,000 48,000 108,000 Logic Modules 768 1,452 2,880 6,036 Combinatorial Cells 512 924 1,800 4,024 Register Cells (Dedicated Flip-Flops) 256 528 1,080 2,012 Maximum Flip-Flops 512 990 1,980 4,024 Maximum User I/Os 130 177 249 360 3 3 3 3 Clocks Quadrant Clocks 0 0 0 4 JTAG Boundary Scan Testing Yes Yes Yes Yes 3.3V/5.0V PCI Yes Yes Yes Yes Clock-to-Out TBD TBD 4.5 ns 4.8 ns Input Set-Up (External) TBD TBD -1.3 ns -3.3 ns Std, -1, -2, -3 Std, -1, -2, -3 Std, -1, -2, -3 Std, -1, -2, -3 C, I, M C, I, M C, I, M C, I, M 208 100, 144 -- 144 208 100, 144 -- 144 208 144 329 144, 256 208 -- -- 484 Speed Grades Temperature Grades Package (by pin count) PQFP TQFP PBGA FBGA S e p t e m b e

Input Tolerance and 5 V Drive Strength Very Low Power Consumption Deterministic, User-Controllable Timing Unique In-System Diagnostic and Verification Capability with Silicon Explorer II Boundary-Scan Testing in Compliance with IEEE 1149.1 (JTAG) A54SX32A A54SX72A Capacity Typical Gates System Gates 32,000 48,000 72,000 108,000 Logic Modules Combinatorial Cells 2,880 1,800 6,036 4,024 Register Cells Dedicated Flip-Flops Maximum Flip-Flops 1,080 1,980 2,012 4,024 Maximum User I/Os 228 213 Global Clocks 3 3 Quadrant Clocks 0 4 Yes Yes Boundary-Scan Testing 3.3 V / 5 V PCI Yes Yes Clock-to-Out 5.3 ns 6.7 ns 0 ns 0 ns Std, -1 Std, -1 84, 208, 256 208, 256 Input Set-Up (External) Speed Grades Package (by Pin Count) CQFP N o ve m b e r 2 0 0 6 (c) 2006 Actel Corporation i See the Actel website for the latest version of the datasheet. HiRel SX-A Family FPGAs Ordering Information A54SX32A - 1 CQ M 208 Application (Ambient Temperature Range) M = Military (-55 to +125C) B = MIL-STD-883 Class B Package Lead