8K2R2J-3-GP R139 8K2R2J-3-GP 2 1 14 CLK_NBHT_CLK 14 CLK_NBHT_CLK# CLK_NBHT_CLK_R CLK_NBHT_CLK#_R 3 4 +3.3V_RUN 1 2 R171 1 14 CLK_NB_14M 2 RN21 SRN2K2J-1-GP RN22 SRN2K2J-1-GP 1 158R2F-GP 4 3 R166 90D9R3F-GP CLK_NB_14M RS780M 1.1V=(90.9/(90.9+158))*3.3V U29 2N7002DW-7F-GP 32 CLK_SCLK S CLK_SCLK D 1 6 G 2 A +3.3V_ALW 2 1 +3.3V_RUN NB OSCIN (14MHz) CLK_SCLK CLK_SDATA SRN0J-6-GP 2 2 DY 3 4 1 CLOCK_EN# 34 RN19 G 2 5 3 4 D A CKG_SMBCLK 34,42 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. S Title 32 CLK_SDATA CKG_SMBDAT 34,42 CLK_SDATA Clock generator ICS9LPR474 Size A3 Document Number 5 4 3 2 Rev FOOSE-AMD 15.4" Date: Friday, January 04, 2008 Sheet 1 SB 6 of 53 5 4 3 2 1 CPU / HT3.0 SSID = CPU D D +1.2V_RUN 1 C184 (1.2V)1.5A for VLDT 2 1 2 1 2 1 2 1 2 1 2 2 C76 SC180P50V2JN-1GP C182 SC180P50V2JN-1GP C74 SCD22U6D3V2KX-1GP C573 SCD22U6D3V2KX-1GP C584 SC4D7U6D3V5KX-3GP B SC4D7U6D3V5KX-3GP SC4D7U6D3V5KX-3GP C 1 Place close to socket C185 U64A D1

C U89F 6 OF 10 VCC CORE 4 +VCCP C202 D 5 6 CRACK_GPIO MCHGND6 MCHGND4 2 5 CRACK_GPIO 3 4 1 6 MCHGND2 2 5 CRACK_GPIO 3 4 CRACK_GPIO 22,31 A MCHGND5 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2N7002DW-7F-GP 2N7002DW-7F-GP Title CRESTLINE(5/6)-PWR/GND Size Document Number Custom Date: Friday, March 30, 2007 Rev PV NORN Sheet 12 of 51 5 U89I A13 A15 A17 A24 AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13 AC3 AC39 AC43 AC47 AD1 AD21 AD26 AD29 AD3 AD41 AD45 AD49 AD5 AD50 AD8 AE10 AE14 AE6 AF20 AF23 AF24 AF31 AG2 AG38 AG43 AG47 AG50 AH3 AH40 AH41 AH7 AH9 AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28 AK31 AK51 AL1 AM11 AM13 AM3 AM4 AM41 AM45 AN1 AN38 AN39 AN43 AN5 AN7 AP4 AP48 AP50 AR11 AR2 AR39 AR44 AR47 AR7 AT10 AT14 AT41 AT49 AU1 AU23 AU29 AU3 AU36 AU49 AU51 AV39 AV48 AW1 AW12 AW16 D C 4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS V

1 2 0_0402_5% FSA +1.05VS_CK505 +3VS_CK505 R123 1 56_0402_5% CLRP1 NO SHORT PADS +3VS +3VS 2.2K_0402_5% V 6 21,27,31,37 ICH_SMBDATA +3VS 2.2K_0402_5% @ C215 5P_0402_50V8C C216 12P_0402_50V8J @ C217 4.7P_0402_50V8C @ C218 4.7P_0402_50V8C Q3A CLK_SMBDATA 1 2N7002DW-7-F_SOT363-6 1 1 SB, MINI PCI R180 10K_0402_5% R179 3 21,27,31,37 ICH_SMBCLK R181 10K_0402_5% Q3B CLK_SMBCLK 4 2 1 CLK_48M_ICH 2 1 CLK_14M_ICH 2 1 CLK_PCI_ICH 2 1 CLK_PCI_EC 2N7002DW-7-F_SOT363-6 2 ho 2008/02/25 2008/02/25 Deciphered Date Title 2 Issued Date 2 Compal Secret Data Security Classification THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMP

16 GND 17 GND 2 GREEN_L 35 SUYIN_070546FR015S265ZR +3VS BLUE_L 35 +CRT_VCC @ SI:change CRT Conn. 2 11,14 CRT_HSYNC RS780 DAC_SCL & SDA is 5V tolerance U14 3 D_HSYNC 4 SN74AHCT1G125GW_SOT353-5 1 L84 2 10_0402_5% HSYNC 1 L83 2 10_0402_5% VSYNC +CRT_VCC Q10A 2N7002DW-7-F_SOT363-6 C857 @ 470P_0402_50V8J 1 1 2 C856 @ 2 470P_0402_50V8J D_DDCCLK 35 @ 5 1 2 11,14 CRT_VSYNC 4 2 D_VSYNC A Y U13 SN74AHCT1G125GW_SOT353-5 3 D_DDCCLK 6 1 C474 1 2 C477 0.1U_0402_16V4Z 2 1 Y P OE# +3VS 11 UMA_CRT_CLK A D_DDCDATA 35 D_HSYNC 1 C470 @ 2 10P_0402_50V8J D_DDCDATA 3 Q10B 2N7002DW-7-F_SOT363-6 10P_0402_50V8J 6.8K_0402_5% G 4 11 UMA_CRT_DAT 1 2 C473 0.1U_0402_16V4Z R218 P OE# 1 2 5 R100 6.8K_0402_5% G +3VS R238 4.7K_0402_5% R237 4.7K_0402_5% 5 1 2 1 +CRT_VCC 35 3 3 D_VSYNC 35 4 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFOR

) Enable SRC0 & 27MHz(DIS) +3VS +3VS R158 2.2K_0402_5% 6 28,32,35 ICH_SMBDATA +3VS 28,32,35 ICH_SMBCLK R178 10K_0402_5% @ C232 2 5P_0402_50V8C @ C233 2 4.7P_0402_50V8C @ C241 2 4.7P_0402_50V8C @ C242 2 4.7P_0402_50V8C @ C243 2 5P_0402_50V8C 3 CLK_SMBCLK 4 2N7002DW-7-F_SOT363-6 Q75B 1 CLK_48M_ICH 1 CLK_14M_ICH 1 CLK_PCI_ICH 1 CLK_PCI_EC 1 CLK_DEBUG_PORT0 A 2 A 2 2.2K_0402_5% CLK_SMBDATA 1 2N7002DW-7-F_SOT363-6 Q75A 1 1 SB, MINI PCI @ R176 10K_0402_5% R159 2 PCI_CLK3 = = = = 5 0 1 0 1 ITP_EN PCI_CLK3 1 1 ITP_EN R179 10K_0402_5% @ R181 10K_0402_5% 2006/02/13 2006/03/10 Deciphered Date Title SCHEMATICS, MB A4082 2 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR

AN217_SC59DAN217_SC59 @ @ 3 2 DAN217_SC59 @ D_DDCCLK RED_L 2 16 GND 17 GND 47 2 GREEN_L 47 BLUE_L 47 SUYIN_070546FR015S265ZR CONN@ SI:change CRT Conn. 1.1 PV MODIFY SI2:change pull high from 6.8K to 2K ohm +3VS_DELAY +CRT_VCC 5 1 A Y U14 D_DDCDATA 47 Q10B 2N7002DW-7-F_SOT363-6 4 D_HSYNC SN74AHCT1G125GW_SOT353-5 1 L84 2 10_0402_5% HSYNC 1 L83 2 10_0402_5% VSYNC +CRT_VCC 1 +3VS RS780 DAC_SCL & SDA is 5V tolerance Q10A 2N7002DW-7-F_SOT363-6 C857 @ 470P_0402_50V8J D_DDCCLK 47 1 1 2 C856 @ 2 470P_0402_50V8J 16 5 1 2 CRT_VSYNC P OE# D_DDCCLK 6 4 2 D_VSYNC A Y U13 SN74AHCT1G125GW_SOT353-5 3 1 @ G 2 M82-S DDC3 & DDC4 is 5V tolerance 16 VGA_DDC_CLK C474 1 2 C477 0.1U_0402_16V4Z D_HSYNC 1 C470 @ 2 3 10P_0402_50V8J D_DDCDATA 3 3 10P_0402_50V8J 1 1 3 2 16,25 CRT_HSYNC 4 16 VGA_DDC_DAT P OE# R218 2K_0402_5% G 5 R100 2K_0402_5% 1 2 1 2 C473 0.1U_0402_16V4Z 2 2 2 1 +CRT_VCC +3VS R238 4.7K_0402_5% @ R237 4.7K_0402_5% @ 47 D_VSYNC 47 4 4 Compal Secret Data Security Classification 2007/08/02 Issued Da

CLK_SDATA SRN0J-6-GP +3.3V_ALW 1 +3.3V_RUN 2 1 2 1 +3.3V_RUN R641 90D9R3F-GP RN49 SRN2K2J-1-GP SRN2K2J-1-GP RN48 Q16 3 4 OSC_14M_NB RS780M 1.1V 158R/90.9R 158R2F-GP R136 2 A 32 CLK_SCLK S CLK_SCLK CLK_SDATA D 1 6 G G 2 5 3 4 D U13 1'nd 84.27002.C3F(DIODES)2N7002DW-7-F 2'nd 84.780SN.A3F(PHILIPS)PMGD780SN 32 3 4 1 14 CLK_NB_14M 2 NB OSCIN (14MHz) Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. S Title 2N7002DW-7F-GP CKG_SMBDAT 34,39 CLK_SDATA A CKG_SMBCLK 34,39 Clock generator ICS9LPR474 Size A3 Document Number 5 4 3 2 Rev FOOSE-14"AMD-SB Date: Saturday, January 05, 2008 Sheet 1 SB 6 of 53 5 4 SSID = CPU 3 2 1 CPU / HT3.0 D D 1 1 2 1 2 1 2 1 2 1 2 2 C104 BOM Change to 62.10040.471 SC180P50V2JN-1GP C157 SC180P50V2JN-1GP C100 SCD22U6D3V2KX-1GP C791 SCD22U6D3V2KX-1GP C789 SC4D7U6D3V5KX-3GP B C797 SC4D7U6D3V5KX-3GP SC4D7U6D3V5KX-3GP C 1 Place close to socket C156 (1.2V)1.5A for VLDT 2 +1.2V_RUN U72A D1 D2 D3 D4 VLDT_A0 VLDT_A1 V

LM15AG121SN1D_0402 L49 1 2 BLM15AG121SN1D_0402 RED +CRT_VCC VSYNC D_DDCCLK RED_L 2 16 GND 17 GND 35 2 GREEN_L 35 +3VS 2 11,14 CRT_HSYNC D_DDCDATA 35 5 1 3 D_HSYNC 4 SN74AHCT1G125GW_SOT353-5 1 L84 2 10_0402_5% HSYNC 1 L83 2 10_0402_5% VSYNC D_DDCCLK 6 Q10A 2N7002DW-7-F_SOT363-6 C857 @ 470P_0402_50V8J 1 1 2 C856 @ 2 470P_0402_50V8J D_DDCCLK 35 2 11,14 CRT_VSYNC 1 @ 5 1 1 2 C477 0.1U_0402_16V4Z 4 C474 2 D_VSYNC A Y U13 SN74AHCT1G125GW_SOT353-5 3 RS780 DAC_SCL & SDA is 5V tolerance U14 +CRT_VCC 2 1 Y P OE# +3VS 11 UMA_CRT_CLK A D_HSYNC 1 C470 @ 2 10P_0402_50V8J D_DDCDATA 3 Q10B 2N7002DW-7-F_SOT363-6 10P_0402_50V8J 6.8K_0402_5% G 4 11 UMA_CRT_DAT 1 2 C473 0.1U_0402_16V4Z R218 P OE# 5 R100 6.8K_0402_5% G +3VS R238 4.7K_0402_5% 1 2 SI:change CRT Conn. +CRT_VCC 2 1 +CRT_VCC R237 4.7K_0402_5% SUYIN_070546FR015S265ZR BLUE_L 35 35 3 3 D_VSYNC 35 4 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P

0MHz 3000mA 0.05ohm DC +CK_VDD_REF 2 1R3F-GP VDDREF VDDCPU VDD48 VDDA R168 X1 1 24 2 Do Not Stuff 1 49 54 65 SC CLK_XTAL_IN +CK_VDD_REF L18 2 1 BLM21PG600SN-1GP +CK_VDD_A VDDSRC VDDSRC VDDSRC VDDSRC CLK_SDATA +3.3V_RUN C225 SC10U6D3V5ZY-2GP 24 9 CLK_SDATA 2N7002DW-7F-GP 2 PG_MODE CLK_SCLK 1 2 1 CLK_SCLK 1 +CK_VDD_MAIN2 2D2R3J-2-GP C675 SCD1U10V2KX-4GP 6 29,36 CKG_SMBCLK D 60ohm 100MHz 3000mA 0.05ohm DC 1 C681 SCD1U10V2KX-4GP 2 C191 SC10U6D3V5ZY-2GP 3 5 C654 SCD1U10V2KX-4GP 4 1+CK_VDD_A 2 C683 SCD1U10V2KX-4GP C682 SCD1U10V2KX-4GP Q17 C662 SCD1U10V2KX-4GP C651 SCD1U10V2KX-4GP 29,36 CKG_SMBDAT R158 +CK_VDD_MAIN 1 2 +CK_VDD_MAIN L12 2 1 BLM21PG600SN-1GP +3.3V_RUN 2 +3.3V_RUN 2 2 SSID = CLOCK 3 2 4 1 5 R573 Do Not Stuff 0 Overclocking of CPU and SRC allowed 1 Overclocking of CPU and SRC not allowed A A 5761 BTPM Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Foose Intel Discrete 5 4 3 2 Size C Document Number Date: Tuesday, April 07, 2009 Rev -1 Cl

ram +3.3V_RUN +3.3V_ALW +3.3V_RUN SRN2K2J-1-GP SRN2K2J-1-GP +3.3V_RUN SRN2K2J-1-GP D ICH8-M SMBCLK SMBDATA ICH_SMBDATA DIMM 1 MEM_SCLK SCL MEM_SDATA CKG_SMBDAT KSO16/GPIOA0/AB1H_CLK CKG_SMBCLK CLK_SDATA SDATA CLK_SCLK SCLK +5V_ALW SMBus address:D2 +5V_RUN 2N7002DW-7F-GP DIMM 2 MEM_SCLK SCL +5V_RUN SRN2K2J-1-GP SMBus Address : A4 AB1A_DATA DOCK_SMBDAT DOCK_SMBCLK AB1A_CLK SMB_CLK WWAN Minicard MEM_SCLK SMB_CLK SMB_DATA SRN2K2J-1-GP (Reverse Type) SDA Express Card MEM_SDATA SMB_DATA C DOCK_SMBDAT_C SIO MEC5025 SMBus address:86 SRN4K7J-8-GP PBAT_SMBDAT C PBAT_SMBCLK +3.3V_SUS ICH_SMBCLK 100R2F-L1-GP-U PBAT_SMBCLK1 100R2F-L1-GP-U PBAT_SMBDAT1 Battery Conn. CLK_SMB DAT_SMB SMBus address:16 WLAN Minicard Capacity Button Board 2N7002DW-7F-GP GPIO86/AB1C_CLK SCLK +3.3V_ALW GPIO87/AB1C_DATA SDATA DOCK_SMBCLK_C +3.3V_WLAN SRN2K2J-1-GP D (Reverse Type) SDA MEM_SDATA ICH_SMBDATA KSO17/GPIOA1/AB1H_DATA SMBus Address : A0 2N7002DW-7F-GP ICH_SMBCLK CLK GEN. SRN4K7J-8-GP ICH_SMBCLK 1 Ch

-GP D SMBDATA ICH_SMBCLK ICH_SMBDATA CLK GEN. SRN4K7J-8-GP ICH8-M SMBCLK 1 DIMM 1 MEM_SCLK SCL MEM_SDATA KSO17/GPIOA1/AB1H_DATA CKG_SMBDAT KSO16/GPIOA0/AB1H_CLK CKG_SMBCLK CLK_SDATA SDATA CLK_SCLK SCLK D (Reverse Type) SDA +5V_ALW SMBus address:D2 +5V_RUN 2N7002DW-7F-GP SMBus Address : A0 2N7002DW-7F-GP DIMM 2 MEM_SCLK SCL MEM_SDATA +5V_RUN SRN2K2J-1-GP SMBus Address : A4 AB1A_DATA DOCK_SMBDAT DOCK_SMBCLK AB1A_CLK Express Card ICH_SMBCLK ICH_SMBDATA SMB_CLK SMB_CLK MEM_SDATA SMB_DATA C DOCK_SMBDAT_C SDATA DOCK_SMBCLK_C SCLK Capacity Button Board SMBus address:86 WWAN Minicard MEM_SCLK SMB_DATA SRN2K2J-1-GP (Reverse Type) SDA 2N7002DW-7F-GP +3.3V_ALW SIO MEC5025 SRN4K7J-8-GP C +3.3V_WLAN Battery Conn. GPIO87/AB1C_DATA PBAT_SMBDAT GPIO86/AB1C_CLK PBAT_SMBCLK +3.3V_SUS SRN2K2J-1-GP ICH_SMBCLK 100R2F-L1-GP-U 100R2F-L1-GP-U PBAT_SMBCLK1 CLK_SMB PBAT_SMBDAT1 DAT_SMB SMBus address:16 WLAN Minicard Charger SMB_CLK SCL +3.3V_ALW SMB_DATA SDA SMBus address:12 2N7002DW-7

46 Pages, 1389 KB, Original