) Enable SRC0 & 27MHz(DIS) +3VS +3VS R158 2.2K_0402_5% 6 28,32,35 ICH_SMBDATA +3VS 28,32,35 ICH_SMBCLK R178 10K_0402_5% @ C232 2 5P_0402_50V8C @ C233 2 4.7P_0402_50V8C @ C241 2 4.7P_0402_50V8C @ C242 2 4.7P_0402_50V8C @ C243 2 5P_0402_50V8C 3 CLK_SMBCLK 4 2N7002DW-7-F_SOT363-6 Q75B 1 CLK_48M_ICH 1 CLK_14M_ICH 1 CLK_PCI_ICH 1 CLK_PCI_EC 1 CLK_DEBUG_PORT0 A 2 A 2 2.2K_0402_5% CLK_SMBDATA 1 2N7002DW-7-F_SOT363-6 Q75A 1 1 SB, MINI PCI @ R176 10K_0402_5% R159 2 PCI_CLK3 = = = = 5 0 1 0 1 ITP_EN PCI_CLK3 1 1 ITP_EN R179 10K_0402_5% @ R181 10K_0402_5% 2006/02/13 2006/03/10 Deciphered Date Title SCHEMATICS, MB A4082 2 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTR
LM15AG121SN1D_0402 L49 1 2 BLM15AG121SN1D_0402 RED +CRT_VCC VSYNC D_DDCCLK RED_L 2 16 GND 17 GND 35 2 GREEN_L 35 +3VS 2 11,14 CRT_HSYNC D_DDCDATA 35 5 1 3 D_HSYNC 4 SN74AHCT1G125GW_SOT353-5 1 L84 2 10_0402_5% HSYNC 1 L83 2 10_0402_5% VSYNC D_DDCCLK 6 Q10A 2N7002DW-7-F_SOT363-6 C857 @ 470P_0402_50V8J 1 1 2 C856 @ 2 470P_0402_50V8J D_DDCCLK 35 2 11,14 CRT_VSYNC 1 @ 5 1 1 2 C477 0.1U_0402_16V4Z 4 C474 2 D_VSYNC A Y U13 SN74AHCT1G125GW_SOT353-5 3 RS780 DAC_SCL & SDA is 5V tolerance U14 +CRT_VCC 2 1 Y P OE# +3VS 11 UMA_CRT_CLK A D_HSYNC 1 C470 @ 2 10P_0402_50V8J D_DDCDATA 3 Q10B 2N7002DW-7-F_SOT363-6 10P_0402_50V8J 6.8K_0402_5% G 4 11 UMA_CRT_DAT 1 2 C473 0.1U_0402_16V4Z R218 P OE# 5 R100 6.8K_0402_5% G +3VS R238 4.7K_0402_5% 1 2 SI:change CRT Conn. +CRT_VCC 2 1 +CRT_VCC R237 4.7K_0402_5% SUYIN_070546FR015S265ZR BLUE_L 35 35 3 3 D_VSYNC 35 4 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY P
SI:change CRT Conn. +3VS RS780 DAC_SCL & SDA is 5V tolerance 5 1 4 D_HSYNC SN74AHCT1G125GW_SOT353-5 1 L84 2 10_0402_5% HSYNC 1 L83 2 10_0402_5% VSYNC 1 1 2 C856 @ 2 470P_0402_50V8J 2 14,16 CRT_VSYNC 4 C474 2 D_VSYNC A Y U13 SN74AHCT1G125GW_SOT353-5 3 Q10A 2N7002DW-7-F_SOT363-6 C857 @ 470P_0402_50V8J D_DDCCLK 43 P OE# D_DDCCLK 6 1 @ 5 1 1 2 C477 0.1U_0402_16V4Z 2 1 U14 +CRT_VCC +3VS M82-S DDC3 & DDC4 is 5V tolerance Y 3 Q10B 2N7002DW-7-F_SOT363-6 16 VGA_DDC_CLK A D_HSYNC D_VSYNC 1 C470 @ 2 3 10P_0402_50V8J 2 14,16,21 CRT_HSYNC D_DDCDATA 43 G 3 6.8K_0402_5% D_DDCDATA 3 10P_0402_50V8J 1 4 16 VGA_DDC_DAT R218 6.8K_0402_5% P OE# 5 R100 1 2 C473 0.1U_0402_16V4Z G +3VS R238 4.7K_0402_5% @ R237 4.7K_0402_5% @ 2 +CRT_VCC 2 1 +CRT_VCC 43 43 4 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY
V_RUN Q74B 2N7002DW-T/R7_SOT363-6~D N21917830 5 +1.05V_VCCP Discharge Circuit R619 100K_0402_5%~D R620 100K_0402_5%~D 2 1 RUN_ON_1.05V# +15V_ALW +3.3V_ALW2 1 2 3 1 2 @ D31 RB751V_SOD323-2~D 1 2 R618 0_0402_5%~D 2 1 2 1 1 D 2 G R617 100K_0402_5%~D 4 2 Q68A 2N7002DW-7-F_SOT363-6~D M_ON_3.3V# C696 4700P_0402_25V7K~D R613 100K_0402_5%~D 6 4 6 1 8 7 6 5 +3.3V_M 3 1 1 +1.05V_M 2 3 2 2 3 G 1 NTMS4107NR2G_SO8~D Q67 +1.05V_M 1 D S 4 M_ENABLE +15V_ALW Discharge Circuit @ Q71 2N7002W-7-F_SOT323-3~D @R615 @ R615 75_0603_5%~D 2 +3.3V_ALW2 @ Q72 2N7002W-7-F_SOT323-3~D @R616 @ R616 1K_0402_5%~D 6 5 2 1 Q68B 2N7002DW-7-F_SOT363-6~D M_ON_3.3V# 5 +3.3V_M R612 20K_0402_5%~D 1 Q66 SI3456BDV-T1-E3_TSOP6~D C694 10U_0805_10V4Z~D 2 +3.3V_ALW R610 100K_0402_5%~D 1 +15V_ALW R611 100K_0402_5%~D A 2 1 +1.05V_VCCP Source +3.3VM Source +3.3V_ALW2 <38> AUX_ON 1 Q64B 2N7002DW-T/R7_SOT363-6~D +3.3V_RUN 2 <37> 3.3V_RUN_ON 2 1 2 3 1 2 @ D30 RB751V_SOD323-2~D 1 2 R609 0_0402_5%~D 2 1 1 8 7 6 5 2 1 R608 100K_0402_5%~D 4
1 2 0_0402_5% FSA +1.05VS_CK505 +3VS_CK505 R123 1 56_0402_5% CLRP1 NO SHORT PADS +3VS +3VS 2.2K_0402_5% V 6 21,27,31,37 ICH_SMBDATA +3VS 2.2K_0402_5% @ C215 5P_0402_50V8C C216 12P_0402_50V8J @ C217 4.7P_0402_50V8C @ C218 4.7P_0402_50V8C Q3A CLK_SMBDATA 1 2N7002DW-7-F_SOT363-6 1 1 SB, MINI PCI R180 10K_0402_5% R179 3 21,27,31,37 ICH_SMBCLK R181 10K_0402_5% Q3B CLK_SMBCLK 4 2 1 CLK_48M_ICH 2 1 CLK_14M_ICH 2 1 CLK_PCI_ICH 2 1 CLK_PCI_EC 2N7002DW-7-F_SOT363-6 2 ho 2008/02/25 2008/02/25 Deciphered Date Title 2 Issued Date 2 Compal Secret Data Security Classification THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMP
16 GND 17 GND 2 GREEN_L 35 SUYIN_070546FR015S265ZR +3VS BLUE_L 35 +CRT_VCC @ SI:change CRT Conn. 2 11,14 CRT_HSYNC RS780 DAC_SCL & SDA is 5V tolerance U14 3 D_HSYNC 4 SN74AHCT1G125GW_SOT353-5 1 L84 2 10_0402_5% HSYNC 1 L83 2 10_0402_5% VSYNC +CRT_VCC Q10A 2N7002DW-7-F_SOT363-6 C857 @ 470P_0402_50V8J 1 1 2 C856 @ 2 470P_0402_50V8J D_DDCCLK 35 @ 5 1 2 11,14 CRT_VSYNC 4 2 D_VSYNC A Y U13 SN74AHCT1G125GW_SOT353-5 3 D_DDCCLK 6 1 C474 1 2 C477 0.1U_0402_16V4Z 2 1 Y P OE# +3VS 11 UMA_CRT_CLK A D_DDCDATA 35 D_HSYNC 1 C470 @ 2 10P_0402_50V8J D_DDCDATA 3 Q10B 2N7002DW-7-F_SOT363-6 10P_0402_50V8J 6.8K_0402_5% G 4 11 UMA_CRT_DAT 1 2 C473 0.1U_0402_16V4Z R218 P OE# 1 2 5 R100 6.8K_0402_5% G +3VS R238 4.7K_0402_5% R237 4.7K_0402_5% 5 1 2 1 +CRT_VCC 35 3 3 D_VSYNC 35 4 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFOR
4 NC_1U_6.3V_Y_Y 0402 PC156 0.01U_25V_M_B 0402 1 2 PR127 100_J 0402 23,34,37,42 RUN_ON 1 2 PR130 100K_F 0402 +5VRUN +8V 8 7 6 5 1 G +5VALW PR188 100K_F 0201 5.3A 4 +3VRUN PQ24 SI4892DY-T1-E3 G S TP138 tpc32t_100 5.5A 1 3 2 1 1 8 7 6 5 S 1 2 +3VALW D PQ48A 2N7002DW-7-F D 2 2 S PC161 0.01U_25V_M_B 0402 2 G 2 2 G 4 1 PR192 100_J 0402 D 5 1 RUN_ON C 6 PQ48B 2N7002DW-7-F PC132 10U_10V_M 0805_X5R 3 100K_F 0201 A6703 A6704 4 2 PR179 TP137 tpc32t_100 3 2 1 G 1 S 1 D PQ20 SI4892DY-T1-E3 1 +5VALW S S PQ46A 2N7002DW-7-F 2 G 2 1 3 D 5 +2_5VRUN D 2V5_RUN_SET D 6 A6702 PC145 10U_10V_M 0805_X5R 5 PR131 100K_F 0402 1 2 23,32,34,42 SUS_ON 100K_F 0201 PC35 10U_6.3V_M 0805_X5R IN OUT GND SHDN# SET 2V5RUN 4 4 2 100K_F 0201 A6701 PQ46B 2N7002DW-7-F 2 PR184 D 1 1 PR185 +3VRUN 1.5A 2 S D 3 1 +5VALW 3 2 1 1 PQ38 SI2304BDS-T1-E3 +8V 200mA PU5 G923-330TIUF TP136 tpc32t_100 2 +3V_S3_SUS +3VALW +5VRUN PC47 10U_10V_M 0805_X5R C +5VRUN_ODD TP163 tpc32t_100 PJ8 S 2N7002EPT 2 2 1 D 4 2 G 1
33 WAKE_SCI# 33 FAN1_PWM 41 DOCK_LED 52 AC_OFF 56 INV_EN_EC 28 IMVP_VR_ON 60 171 FAN1_TACH FAN1_TACH 41 +ECVCC R1437 NC_10K_J 0402 1 5 G SIO_FD[7..0] 38 FRD# 38 FWR# 38 30MIL TP255 MEMCS# 38,39 54 55 41 23 3,32,38,39,57 0402 2 10K_J 0402 R1442 Q102A S NC_2N7002DW-7-F Q102B R1440 NC_10K_J 0402 CN12 SMDFIX2 S NC_2N7002DW-7-F R1439 NC_10K_J 0402 ALW_ON 56,57 1 4.7K_J JIG_SMI# 1 D D 2 G 0402 DAT_SMB 2 R699 D_S5_PWRGD_EC 3 R1438 NC_10K_J 0402 52 D_S5_PWRGD EC don't use this pin ; left N.C is OK +ECVCC SMB_THRM_CLK 3,22 SMB_THRM_DATA 3,22 CLK_SMB 56 DAT_SMB 56 A 1 4.7K_J 1 163 164 169 170 1 SCL1 GPWU0 SDA1 GPWU1 SCL2 GPWU2 SDA2 GPWU3 GPWU4 PWM0/GPOW0 GPWU5 PWM1/GPOW1 GPWU6/TIN1 PWM2/GPOW2/FAN1PWM GPWU7/TIN2/FANFB2 PWM3/GPOW3 PWM4/GPOW4 PSCLK1 PWM5/GPOW5 PSDAT1 PWM6/GPOW6 PSCLK2 PWM7/GPOW7/FAN2PWM PSDAT2 PSCLK3 PSDAT3 FANFB1/TOUT1/GPIO2E AD0/GPIAD0 AD1/GPIAD1 AD2/GPIAD2 AD3/GPIAD3 CAPLOCK#/GPIO11 AD4/GPIAD4 FNLOCK#/GPIO12 AD5/GPIAD5 SCROLLLOCK#/GPIO0F AD6/GPIAD6 NUMLOCK#/GPIO0A AD7/GPIAD7
AG121SN1D_0402 RED +CRT_VCC VSYNC D_DDCCLK 16 17 2 CONN@ SUYIN_070546FR015S263ZR +3VS +CRT_VCC 2 R218 2.2K_0402_5% <14,16,21> CRT_HSYNC 6 2 A G 1 1 1 5 1 R100 2.2K_0402_5% 1 2 D_DDCDATA 4 D_HSYNC L84 1 0_0603_5% 2 HSYNC U14 SN74AHCT1G125GW_SOT353-5 3 Q10A 2N7002DW-7-F_SOT363-6 Y 5 <16> VGA_DDC_DAT 1 2 C473 0.1U_0402_16V4Z P OE# R238 4.7K_0402_5% 2 2 2 1 +CRT_VCC R237 4.7K_0402_5% 2 470P_0402_50V8J 3 2 Y 4 D_ VSYNC L83 1 0_0603_5% 2 VSYNC U13 SN74AHCT1G125GW_SOT353-5 1 @ C474 1 @ C470 2 2 10P_0402_50V8J <14,16> CRT_VSYNC @ C856 3 470P_0402_50V8J 1 2 @ C477 0.1U_0402_16V4Z 2 A 10P_0402_50V8J @ C857 1 P OE# 1 5 1 D_DDCCLK 4 3 Q10B 2N7002DW-7-F_SOT363-6 G <16> VGA_DDC_CLK 3 4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE I
AN217_SC59DAN217_SC59 @ @ 3 2 DAN217_SC59 @ D_DDCCLK RED_L 2 16 GND 17 GND 47 2 GREEN_L 47 BLUE_L 47 SUYIN_070546FR015S265ZR CONN@ SI:change CRT Conn. 1.1 PV MODIFY SI2:change pull high from 6.8K to 2K ohm +3VS_DELAY +CRT_VCC 5 1 A Y U14 D_DDCDATA 47 Q10B 2N7002DW-7-F_SOT363-6 4 D_HSYNC SN74AHCT1G125GW_SOT353-5 1 L84 2 10_0402_5% HSYNC 1 L83 2 10_0402_5% VSYNC +CRT_VCC 1 +3VS RS780 DAC_SCL & SDA is 5V tolerance Q10A 2N7002DW-7-F_SOT363-6 C857 @ 470P_0402_50V8J D_DDCCLK 47 1 1 2 C856 @ 2 470P_0402_50V8J 16 5 1 2 CRT_VSYNC P OE# D_DDCCLK 6 4 2 D_VSYNC A Y U13 SN74AHCT1G125GW_SOT353-5 3 1 @ G 2 M82-S DDC3 & DDC4 is 5V tolerance 16 VGA_DDC_CLK C474 1 2 C477 0.1U_0402_16V4Z D_HSYNC 1 C470 @ 2 3 10P_0402_50V8J D_DDCDATA 3 3 10P_0402_50V8J 1 1 3 2 16,25 CRT_HSYNC 4 16 VGA_DDC_DAT P OE# R218 2K_0402_5% G 5 R100 2K_0402_5% 1 2 1 2 C473 0.1U_0402_16V4Z 2 2 2 1 +CRT_VCC +3VS R238 4.7K_0402_5% @ R237 4.7K_0402_5% @ 47 D_VSYNC 47 4 4 Compal Secret Data Security Classification 2007/08/02 Issued Da
6P_0402_50V8K 16 2 DAN217_SC59DAN217_SC59 @ @ 3 2 DAN217_SC59 @ D_DDCCLK RED_L 2 16 GND 17 GND 43 2 GREEN_L 43 BLUE_L 43 SUYIN_070546FR015S265ZR CONN@ SI:change CRT Conn. SI2:change pull high from 6.8K to 2K ohm +3VS +CRT_VCC 5 1 A Y U14 D_DDCDATA 43 Q10B 2N7002DW-7-F_SOT363-6 D_HSYNC 4 SN74AHCT1G125GW_SOT353-5 1 L84 2 10_0402_5% HSYNC 1 L83 2 10_0402_5% VSYNC +CRT_VCC 1 +3VS RS780 DAC_SCL & SDA is 5V tolerance Q10A 2N7002DW-7-F_SOT363-6 C857 @ 470P_0402_50V8J D_DDCCLK 43 1 1 2 C856 @ 2 470P_0402_50V8J 16 5 1 2 CRT_VSYNC P OE# D_DDCCLK 6 4 2 D_VSYNC A Y U13 SN74AHCT1G125GW_SOT353-5 3 1 @ G 2 M82-S DDC3 & DDC4 is 5V tolerance 16 VGA_DDC_CLK C474 1 2 C477 0.1U_0402_16V4Z D_HSYNC 1 C470 @ 2 3 10P_0402_50V8J D_DDCDATA 3 3 10P_0402_50V8J 1 1 3 2 16,21 CRT_HSYNC 4 16 VGA_DDC_DAT P OE# R218 2K_0402_5% G 5 R100 2K_0402_5% 1 2 1 2 C473 0.1U_0402_16V4Z 2 2 2 1 +CRT_VCC +3VS R238 4.7K_0402_5% @ R237 4.7K_0402_5% @ 43 D_VSYNC 43 4 4 Compal Secret Data Security Classification 2007/08/02 Issued Da
V_RUN Q74B 2N7002DW-T/R7_SOT363-6~D N21917830 5 +1.05V_VCCP Discharge Circuit R619 100K_0402_5%~D R620 100K_0402_5%~D 2 1 RUN_ON_1.05V# +15V_ALW +3.3V_ALW2 1 2 3 1 2 @ D31 RB751V_SOD323-2~D 1 2 R618 0_0402_5%~D 2 1 2 1 1 D 2 G R617 100K_0402_5%~D 4 2 Q68A 2N7002DW-7-F_SOT363-6~D M_ON_3.3V# C696 4700P_0402_25V7K~D R613 100K_0402_5%~D 6 4 6 1 8 7 6 5 +3.3V_M 3 1 1 +1.05V_M 2 3 2 2 3 G 1 NTMS4107NR2G_SO8~D Q67 +1.05V_M 1 D S 4 M_ENABLE +15V_ALW Discharge Circuit @ Q71 2N7002W-7-F_SOT323-3~D @R615 @ R615 75_0603_5%~D 2 +3.3V_ALW2 @ Q72 2N7002W-7-F_SOT323-3~D @R616 @ R616 1K_0402_5%~D 6 5 2 1 Q68B 2N7002DW-7-F_SOT363-6~D M_ON_3.3V# 5 +3.3V_M R612 20K_0402_5%~D 1 Q66 SI3456BDV-T1-E3_TSOP6~D C694 10U_0805_10V4Z~D 2 +3.3V_ALW R610 100K_0402_5%~D 1 +15V_ALW R611 100K_0402_5%~D A 2 1 +1.05V_VCCP Source +3.3VM Source +3.3V_ALW2 <38> AUX_ON 1 Q64B 2N7002DW-T/R7_SOT363-6~D +3.3V_RUN 2 <37> 3.3V_RUN_ON 2 1 2 3 1 2 @ D30 RB751V_SOD323-2~D 1 2 R609 0_0402_5%~D 2 1 1 8 7 6 5 2 1 R608 100K_0402_5%~D 4
9 2.2K_0402_5% @ C215 2 5P_0402_50V8C @ C216 2 4.7P_0402_50V8C @ C217 2 4.7P_0402_50V8C @ C218 2 4.7P_0402_50V8C @ C219 2 5P_0402_50V8C 2 PCI_CLK3 0 = SRC8/SRC8# 1 = ITP/ITP# 0 = Enable DOT96 & SRC1(UMA) 1 = Enable SRC0 & 27MHz(DIS) 5 ITP_EN CLK_SMBDATA 1 2N7002DW-7-F_SOT363-6 CLK_SMBCLK 4 2N7002DW-7-F_SOT363-6 1 C LK_48M_ICH 1 C LK_14M_ICH 1 CL K _ PCI_ICH 1 CL K_PCI_EC 1 CLK_DEBUG_PORT_0 2 A 2 A P CI_CLK3 1 1 ITP_EN @ R182 10K_0402_5% R183 10K_0402_5% 2007/08/28 2006/03/10 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Compal Electronics, Inc. Cl
CLRP1 NO SHORT PADS +3VS +3VS PCI_CLK3 +3VS #SI change to 33 ohm R178 2.2K_0402_5% V 6 21,27,31,37 ICH_SMBDATA +3VS R180 10K_0402_5% R179 2.2K_0402_5% @ C215 5P_0402_50V8C C216 12P_0402_50V8J @ C217 4.7P_0402_50V8C @ C218 4.7P_0402_50V8C Q3A CLK_SMBDATA 1 2N7002DW-7-F_SOT363-6 1 SB, MINI PCI 1 #PV for WWAN noise add 12P +3VS V 5 ITP_EN 2 0 = SRC8/SRC8# 1 = ITP/ITP# 0 = Enable DOT96 & SRC1(UMA) 1 = Enable SRC0 & 27MHz(DIS) 3 21,27,31,37 ICH_SMBCLK R181 10K_0402_5% Q3B CLK_SMBCLK 4 2 1 CLK_48M_ICH 2 1 CLK_14M_ICH 2 1 CLK_PCI_ICH 2 1 CLK_PCI_EC 2N7002DW-7-F_SOT363-6 2 A 2 A @ R182 10K_0402_5% PCI_CLK3 1 1 ITP_EN @ R183 10K_0402_5% 2008/02/25 2008/02/25 Deciphered Date Title 2 Issued Date 2 Compal Secret Data Security Classification THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTH
16 GND 17 GND 2 GREEN_L 35 SUYIN_070546FR015S265ZR +3VS BLUE_L 35 +CRT_VCC @ SI:change CRT Conn. 2 11,14 CRT_HSYNC RS780 DAC_SCL & SDA is 5V tolerance U14 3 D_HSYNC 4 SN74AHCT1G125GW_SOT353-5 1 L84 2 10_0402_5% HSYNC 1 L83 2 10_0402_5% VSYNC +CRT_VCC Q10A 2N7002DW-7-F_SOT363-6 C857 @ 470P_0402_50V8J 1 1 2 C856 @ 2 470P_0402_50V8J D_DDCCLK 35 @ 5 1 2 11,14 CRT_VSYNC 4 2 D_VSYNC A Y U13 SN74AHCT1G125GW_SOT353-5 3 D_DDCCLK 6 1 C474 1 2 C477 0.1U_0402_16V4Z 2 1 Y P OE# +3VS 11 UMA_CRT_CLK A D_DDCDATA 35 D_HSYNC 1 C470 @ 2 10P_0402_50V8J D_DDCDATA 3 Q10B 2N7002DW-7-F_SOT363-6 10P_0402_50V8J 6.8K_0402_5% G 4 11 UMA_CRT_DAT 1 2 C473 0.1U_0402_16V4Z R218 P OE# 1 2 5 R100 6.8K_0402_5% G +3VS R238 4.7K_0402_5% R237 4.7K_0402_5% 5 1 2 1 +CRT_VCC 35 3 3 D_VSYNC 35 4 4 Compal Secret Data Security Classification 2007/08/02 Issued Date 2008/08/02 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFOR