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Xilinx.com/XC3090-100CB164B
{"VIH Min. (CMOS) (V)":"3.5","V(OL)Max.(V)Lo Level Out.Volt.":"0.4","Digital Input V Max (V)":"7.5","Vsup(+) Nom.(V) Pos.Sup.Volt.":"5","Quiescent Current Max (TTL)":"15m","Pins":"N/A","@Iol (A)":"4.0m","Logic Level Family":"CMOS and T","Quiescent Current Max (CMOS)":"3m","Package Body Material":"Ceramic","Gate Capacity":"9000","VIL Max. (TTL) (V)":"0.8","Package":"QFP","VIH Min. (TTL) (V)":"2.0","@IOH (test)":"4m","Configurable Logic Blocks":"320","VIL Max. (CMOS) (V)":"1.0","Military":"N","Mil Number":"59...
1229 Bytes - 20:39:05, 16 November 2024
Xilinx.com/XC3090-100CB164B(SMD)
{"VIH Min. (CMOS) (V)":"3.5","V(OL)Max.(V)Lo Level Out.Volt.":"0.4","Digital Input V Max (V)":"7.5","Vsup(+) Nom.(V) Pos.Sup.Volt.":"5","Quiescent Current Max (TTL)":"15m","Pins":"N/A","@Iol (A)":"4.0m","Logic Level Family":"CMOS and T","Quiescent Current Max (CMOS)":"3m","Package Body Material":"Ceramic","Gate Capacity":"9000","VIL Max. (TTL) (V)":"0.8","Package":"QFP","VIH Min. (TTL) (V)":"2.0","@IOH (test)":"4m","Configurable Logic Blocks":"320","VIL Max. (CMOS) (V)":"1.0","Military":"Y","Mil Number":"59...
1258 Bytes - 20:39:05, 16 November 2024

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