CY7C131-55JCT SRAM Chip Async Dual 5V 8K-Bit 1K x 8 55ns 52-Pin PLCC T/R
From CYPRESS SEMICONDUCTOR
| Access Time | 55ns |
| Access Time (Max) | 55ns |
| Address Bus | 20 b |
| Architecture | Not Required |
| Clock Freq | Not Required MHz |
| Clock Freq (Max) | Not Required MHz |
| Density | 8192 Bit |
| Mounting | Surface Mount |
| Number of Ports | 2 |
| Number of Words | 1K word |
| Operating Supply Voltage (Max) | 5.5 V |
| Operating Supply Voltage (Min) | 4.5 V |
| Operating Supply Voltage (Typ) | 5 V |
| Operating Temp Range | 0C to 70C |
| Operating Temperature Classification | Commercial |
| Package Type | PLCC |
| Packaging | Tape and Reel |
| Pin Count | 52 |
| Rad Hardened | No |
| Supply Current | 110mA |
| Sync/Async | Asynchronous |
| Word Size | 8 b |
